The exemplary embodiments relate to a single damascene interconnect structure and particularly relate to a single damascene interconnect structure in which a via and a trench are formed by separate single damascene processes and only one of the via and trench has a robust refractory barrier layer such as Ta/TaN.
Integrated circuits generally comprise barrier layers at the interface between a conductive layer (typically a metal line or via in a multilayered interconnect structure) and an insulating layer (typically a dielectric layer in such a structure). These barrier layers prevent the diffusion of atoms from the conductive zone to the insulating zone, which can be the origin of integrated circuit malfunctions such as short-circuits between metal lines.
A typical method of forming a barrier layer for an integrated circuit involves forming a via and an overlay trench, by a dual damascene process, in a dielectric. The via and trench are then lined with a barrier layer of a refractory material, such as TiN, Ta, TaN or their combinations. The barrier layer serves to inhibit the diffusion of the interconnection material that will subsequently be introduced in the via and trench into the dielectric. Next, a suitable seed layer is deposited on the wall or walls of the via and trench. Suitable seed materials for the deposition of Cu interconnection material may include Cu. Interconnection material, such as Cu, is then deposited by electroplating or physical deposition in a sufficient amount to fill the via and the trench.